1. Field of the Invention
The present invention relates to an insulated gate semiconductor device for controlling a large power, in particular to a semiconductor device which is called xe2x80x9ca power MOS devicexe2x80x9d and a method of manufacturing the same. Representatively, there are a power MOS FET (hereinafter referred to simply as xe2x80x9cpower MOSxe2x80x9d) which is an MOS gate device, an IGBT (insulated gate bipolar transistor), etc.
2. Description of the Related Art
In recent years, the semiconductor devices have been tended to be made more fine so that the machining dimensions of a deep sub-micron region are required. However, there has been known that, in the MOS FET, when a channel formation region is identical in dimension with the deep sub-micron region, there arises a problem such as the phenomenon of a short channel effect.
The short channel effect is the phenomenon developed because the charges in the channel formation region are largely influenced by not only a gate voltage but also the charges in a depletion layer of a source/drain region, an electric field and a potential distribution as the line width of a gate electrode is shortened, that is, a channel formation region is shortened. There has been known that the short channel effect leads to a variety of problems such as the lowering of a threshold value voltage, the deterioration of a sub-threshold characteristic, the deterioration of a withstand voltage, and so on.
The problem of the above phenomenon is common to all of the device having an MOS structure that operates with the formation of a channel. This is also seen in the power MOS device for controlling a large power without exception. There are many cases in which the power MOS device requires a high withstand voltage because there are used a large current and a large voltage, and therefore the deterioration of a withstand voltage caused by the short channel effect leads to a large problem.
In general, the power MOS device is directed to a semiconductor device which is used as a switching device of an electronic equipment, or the like, and the power devices of a high-speed MOS such as a power MOS or an IGBT have been known as examples. These semiconductor devices are characterized in that they are different in structure from an IC or an LSI because a large voltage and a large current are used.
A basic structure of a single cell of the power MOS is shown in FIG. 2. In the figure, marks represented by xe2x80x9c+xe2x80x9d or xe2x80x9cxe2x88x92xe2x80x9d are used as an index representing the relative strength of conductivity. In other words, for example, n+ represents n-type stronger than nxe2x88x92.
In FIG. 2, a weak n-type (nxe2x88x92) region 202 that is called xe2x80x9ca drift regionxe2x80x9d is formed on a semiconductor substrate 201 having an n+-type through an epitaxial growth. The semiconductor substrate 201 having the n+-type functions as a drain region as it is.
Also, a strong p-type (p+) region 203 is formed on the drift region 203 through an impurity diffusion, and a source region 204 having the n+-type is also disposed therein. A part of the strong p-type (p+) region 203, which is located immediately under a gate electrode, functions as a channel formation region. Then, it is structured such that a gate electrode 206 is disposed on a semiconductor surface through a gate insulating film 205.
In case of the power MOS structure of this type, when a positive voltage is applied to the gate electrode 206, a channel region 207 is formed in the p-type region (channel formation region) 203 in the vicinity of the gate electrode 206 so that a current flows in a direction indicated by an arrow (in case of the enhancement n-channel FET).
In this way, the MOS IC used for an IC or an LSI is structured such that a current flows laterally in the vicinity of the surface of the semiconductor substrate, whereas the power MOS shown in FIG. 2 is characterized in that source/drain regions are disposed so as to sandwich the semiconductor substrate therebetween so that a current flows vertically.
The reason why the power MOS is structured such that a current flows vertically as described above is that an on-state resistance (a resistant value of all the regions in which a drain current flows) is reduced to increase a current density. This is one of important structures for the power MOS which allows a large current to flow therein and performs a high-speed operation.
Hence, in the case where a high-speed operation characteristic is required, it is desirable that a resistively of the drift region is small, but on the contrary, in the case where a high withstand voltage characteristic is required, it is devised that the resistively of the drift region is made large to improve the withstand voltage.
However, in the case where the high-speed operation characteristic is required, when the resistively of the drift region is made small, there may arise such a problem that the device is destroyed because the withstand voltage exceeds a limit when the withstand voltage is deteriorated by the short channel effect.
A state where the short channel effect is developed in the power MOS is simplified and shown in FIG. 3. FIG. 3 represents an enlarged diagram of the periphery of the channel region 207 shown in FIG. 2.
In FIG. 3, reference numeral 301 denotes a drift region formed of a weak n-type (nxe2x88x92); 302 is a channel formation region formed of a strong p-type (p+); 303 is a source region formed of a strong n-type (n+); 304 is a channel region; and 305 is a gate electrode. Also, a dotted line indicated by reference numeral 306 represents a depletion layer formed when the drain voltage is small.
Normally, a current that flows in the channel region 304 is controlled by only the gate voltage. In this case, as indicated by reference numeral 306, the depletion layer in the vicinity of the channel region 304 is disposed substantially in parallel with the channel to form a uniform electric field.
However, as the drain voltage becomes high, the depletion layer in the vicinity of the drift region 301 extends toward the channel region 3,04 and the source region 303 so that, as represented by a solid line 307, the charges or the electric field of the drain depletion layer adversely affect the depletion layer in the vicinity of the source region 303 and the channel region 304. In other words, an on-state current is varied by the complicated distribution of the electric field, thereby leading to a circumstance where it is difficult to control the current which flows in the source region 303 and the channel region 304 by only the gate voltage.
An energy state of the periphery of the channel formation region in the case where the short channel effect is developed will be described with reference to FIG. 4. In FIG. 4, respective illustrations of states indicated by solid lines show an energy band in the vicinity of the source region 401, the p-type region (channel formation region) 402 and the drift region 403 when the drain voltage is 0 V.
In that state, when a sufficiently large drain voltage Vd is applied, the states indicated by the solid lines are changed into states indicated by dotted lines in FIG. 4. In other words, the charges and the electric field in the depletion layer of the drift region which are formed by the drain voltage Vd adversely affect the charges in the depletion layers of the source and channel formation regions 401 and 402, with the result that the energy (potential) state changes continuously from the source region 401 to the drift region 403.
Then, as an influence of the short channel effect on the semiconductor device, there occurs the lowering of the threshold value voltage (Vth) and the punch-through phenomenon. Also, when an influence of the gate voltage on the drain current is lowered by the punch-through phenomenon, the sub-threshold characteristic is deteriorated.
First, the lowering of the threshold value voltage is a phenomenon that occurs in the n-channel FET as well as the p-channel FET. Also, the degree of the lowering depends not only on the drain voltage, but also on a variety of parameters such as the concentration of the impurities in the substrate, the depth of the source/drain diffusion layers, the thickness of the gate oxide film, the substrate bias, and so on.
Although the lowering of the threshold value voltage is desirable from the viewpoint that it makes the power consumption small, it generally leads to a problem that the frequency characteristic does not become high because the drive voltage of the integrated circuit becomes small.
For that reason, up to now, it is general that as means for controlling the threshold value voltage, impurity elements that give one conductivity are uniformly added to the whole channel formation region, and the threshold value voltage is controlled with the amount of the impurity elements as added. However, even this method cannot prevent the short channel effect per se, whereby the punch-through phenomenon and so on are caused to occur. Also, since the impurities as added scatter the carriers, they cause the mobility of the carriers to be lowered.
Also, the deterioration of the sub-threshold characteristic which is caused by the punch-through phenomenon means that the sub-threshold coefficient (S-value) increases, that is, the switching characteristic of the FET is deteriorated. An influence of the short-channel effect on the sub-threshold characteristic is shown in FIG. 5.
FIG. 5 is a graph whose horizontal axis represents the gate voltage Vg, and whose vertical axis represents the logarithm of the drain current Id, and the inverse number of a slope (the sub-threshol d characteristic) in the region 501 is the S-value. In FIG. 5, changes of the characteristics when the channel length is gradually shortened are compared, and the channel length is shortened toward a direction indicated by an arrow.
As a result, the slope of the characteristic becomes small as the channel length is shortened. In other words, it can be confirmed that there is a tendency that the S-value is increased. This means that the switching characteristic of the semiconductor device is more deteriorated as the channel length is shortened.
As described above, the phenomenon of the short channel effect is a serious problem even in the power MOS device, and a problem to be solved for making the semiconductor device fine in the future.
In particular, in the power MOS device, the high-speed operation characteristic and the high-withstand voltage characteristic have a relation of a trade-off, and in the case where an importance is given to the high-speed operation characteristic, the deterioration of the withstand voltage which is caused by the short channel effect is remarkable as a problem of the destruction of device.
The present invention has been made in view of the above circumstances, and therefore an object of the present invention is to provide an insulated gate semiconductor device that realizes both of the high-speed operation characteristic and the high-withstand voltage characteristic simultaneously, in particular, a power MOS device and a method of manufacturing the same.
In order to solve the above problem, according to one aspect of the present invention, there is provided an insulated gate semiconductor device, comprising:
a source region, a drain region, a drift region and a channel formation region, which are formed using a crystal semiconductor; and
a gate insulating film and a gate electrode formed on said channel formation region;
wherein said channel formation region includes a region in which carriers move, and an impurity region artificially and locally formed for pining a depletion layer that extends from said drift region toward said channel formation region and said source region.
According to another aspect of the present invention, there is provided an insulated gate semiconductor device, comprising:
a source region, a drain region, a drift region and a channel formation region, which are formed using a crystal semiconductor; and
a gate insulating film and a gate electrode formed on said channel formation region;
wherein said channel formation region includes a region in which carriers move, and an impurity region artificially and locally formed for controlling to a predetermined threshold value voltage by addition of impurity elements.
In the present specification, the crystal semiconductor is, as a representative example, a monocrystal silicon with a grade which is normally used in the level of the existing IC and VLSI, but also includes a monocrystal silicon with a higher grade (to the extreme, monocrystal silicon in an ideal state such that it is fabricated in space).
The subject matter of the present invention is to effectively restrain the expansion of a depletion layer from the drift region toward the channel formation region by an impurity region which is artificially locally formed in the channel formation region, thereby preventing a variety of problems such as the punch-through phenomenon and the deterioration of the sub-threshold characteristic and the deterioration of the withstand voltage, which are caused by the short channel effect.
Since the device of the present invention is formed as if pins of an impurity region are formed in the channel formation region, the present applicant calls the device xe2x80x9cpining type power MOS devicexe2x80x9d. In the present specification, xe2x80x9cpiningxe2x80x9d means xe2x80x9crestraintxe2x80x9d, and xe2x80x9cpinxe2x80x9d means xe2x80x9crestrainxe2x80x9d.
In other words, the impurity region is locally formed in the channel formation region, and that region is used as an energy barrier. Using the impurity region as the energy barrier, the depletion layer on the drift region side is energy-restrained from extending toward the channel formation region side, whereby an electric field formed in the channel formation region is controlled by only the gate voltage.
In the present invention, there are used impurity elements that extend the energy band width (Eg) as the impurity elements that form the impurity region for achieving the above structure. The impurity elements of this type are one kind or a plurality of kinds selected from carbon (C), nitrogen (N) and oxygen (O).
In this case, the added impurities form an energy barrier which is locally large in an energy band width within the channel formation region. In the case of using carbon, nitrogen or oxygen as in the present invention, the energy band which was in a state shown in FIG. 6A becomes a state shown in FIG. 6B, and the energy band width (Eg) is widened whereby the barrier xcex94 E further increases to the barrier xcex94 AExe2x80x2. For example, in the case where oxygen is added, it becomes an insulating high-resistant region having a structure represented by SiOx, which forms an electrically barrier.
Also, impurity elements can be used which allow the energy band width to be shifted other than the above impurity elements. The impurity elements of this type are the elements of group XIII (representatively, boron) and the elements of group XV (representatively, phosphorus or arsenic). In the present invention, the elements of group XIII are used in the case of manufacturing the n-channel power MOS, and the elements of group XV are used in the case of manufacturing the p-channel power MOS.
In both the cases, since the channel formation region and the impurity region are identical in conductive type with each other, it is desirable that the impurity region is set to be higher than the channel formation region. Also, in the case where the channel formation region is substantially intrinsic, the concentration of the impurity region can be lowered.
The impurity region added with these impurity elements function to change the energy band configuration of the channel region and to either increase or reduce the threshold voltage. Accordingly, the concentration of the added impurity in the impurity region should be sufficiently high to at least control the threshold voltage, for example, 1xc3x971017 to 1xc3x971020 atoms/cm3, preferably, 1xc3x971018 to 1xc3x971019 atoms/cm3.
The concentration of the impurity should be at least 100 times as high as the impurity concentration of the substrate (in a typical single crystal silicon substrate, it is about 1xc3x971015/cm3), hence, 1xc3x971017/cm3 is the lower limit. Also, if the concentration exceeds 1xc3x971020 atoms/cm3, it is not desirable in view of the burden of the device.
Also, it is desirable to activate the added impurity element by furnace annealing, laser annealing or lamp annealing, or the like. Care should be taken to suppress the thermal diffusion of the impurity during the annealing. For example, the sufficient activation can be achieved by the furnace annealing at 500-800xc2x0 C. (preferably, 600-700xc2x0 C.) While suppressing the thermal diffusion.
The substrate may be heated during the ion implantation in order to simultaneously activate the impurity. Also, the activation efficiency can be improved by increasing an RF power of the ion implantation. This may be used solely or in combination with the foregoing annealing step.
In this case, the impurities added locally shifts the energy band in the channel formation region. For example, in the case where boron is added to the n-channel power MOS, the energy band which was in a state shown in FIG. 7A is changed into a state shown in FIG. 7B, and the Fermi level (Ef) is shifted so that the barrier xcex94 E further increases to the barrier xcex94 Exe2x80x2. It is needless to say that in this case, the shifting of the Fermi level is resultantly nothing other than the shifting of the energy band of the channel formation region.
Also, that region has an inverse conductivity to the channel region, and forms a sufficient energy barrier although it is low in resistant value. Similarly, in the case where phosphorus or arsenic is added to the p-channel power MOS, an inverse conductive region is formed so that it can be applied as an energy barrier.
According to yet still another aspect of the present invention, there is provided an insulated gate semiconductor device, comprising:
a source region, a drain region, a drift region and a channel formation region, which are formed using a crystal semiconductor; and
a gate insulating film and a gate electrode formed on said channel formation region;
wherein said channel formation region includes a region in which carriers move, and an impurity region artificially and locally formed for pining a depletion layer that extends from said drift region toward said channel formation region and said source region, and for regulating a carrier moving path by said impurity region.
Also, according to yet still another aspect of the present invention, there is provided an insulated gate semiconductor device, comprising:
a source region, a drain region, a drift region and a channel formation region, which are formed using a crystal semiconductor; and
a gate insulating film and a gate electrode formed on said channel formation region;
wherein said channel formation region includes a region in which carriers move, and an impurity region artificially and locally formed for controlling to a predetermined threshold value voltage by addition of impurity elements, and for regulating a carrier moving path by said impurity region.
The impurity regions can be provided in the form of a dot pattern or in the form of a linear pattern within the channel formation region. In particular, in the case where the impurity regions are provided in the form of a linear pattern which is substantially in parallel with the channel direction (a direction along which the carriers move), the impurity regions form side walls that function as rails along which the carriers move. As a result, because the carrier moving path is regulated, there is obtained an advantage that the possibility of scattering caused by the collision of the carriers with each other is reduced to improve the mobility.
As described above, with the formation of the impurity regions being artificially and locally formed in the channel formation region, the region in which the carriers move and the impurity regions for pining the depletion layer that extends from the drift region toward the channel formation region are disposed in the same channel formation region, thereby being capable of preventing the deterioration of various characteristics which are caused by the short channel effect.
Also, the lowering of the threshold value voltage which is a representative phenomenon caused by the short channel effect which is accompanied by the fining of the channel length is relieved by artificially developing the narrow channel effect between the respective impurity regions. This is also one of the significant structures of the present invention.
The narrow channel effect is a phenomenon that develops phenomenons such as an increase of the threshold value voltage by narrowing the channel formation region, and frequently leads to a problem in the MOS IC. The present invention has an effect that the narrow channel effect is intentionally developed using this phenomenon to control the threshold value voltage so that the lowering the threshold value voltage accompanied by the short channel effect is offset.
Also, according to yet still another aspect of the present invention, there is provided a method of manufacturing an insulated gate semiconductor device, said method comprising the steps of:
forming a source region, a drain region, a drift region and a channel formation region, using a crystal semiconductor;
artificially and locally forming impurity regions in said channel formation region; and
forming a gate insulating film and a gate electrode on said channel formation region;
wherein said channel formation region is composed of a region in which carriers move, and said impurity regions; and
wherein impurity elements that extend an energy band width (Eg) are artificially and locally added in said impurity regions.
Further, according to yet still another aspect of the present invention, there is provided a method of manufacturing an insulated gate semiconductor device, said method comprising the steps of:
forming a source region, a drain region, a drift region and a channel formation region, using a crystal semiconductor;
artificially and locally forming impurity regions in said channel formation region; and
forming a gate insulating film and a gate electrode on said channel formation region;
wherein said channel formation region is composed of a region in which carriers move, and said impurity regions; and
wherein impurity elements that shift an energy band width (Eg) are artificially and locally added in said impurity regions.